PCIe Endpoint to Endpoint data transfer

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TRINATH KARRI

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Hi,

I have a PCIe Rootcomplex (Custom LS1046A board configured as RC), Endpoint-1 (Custom LS1046A board configured as EP) and Endpoint-2 (Custom IMX8QM board configured as EP). Endpoints are connected to the Root complex through switch (PI7C9X2G1224GP).

I want to perform Endpoint-1 to Endpoint-2 data transfer. For that, i configured ATU registers of Endpoint-1 and Endpoint-2 as mentioned below.

Endpoint-1:

#BAR-0 region-0 as Inbound
0x0340_1010 = 0x00000FFF -- BAR0 mask register
0x0340_0900 = 0x80000000 -- iATU Index register
0x0340_0908 = 0xC0000000 -- iATU Region Control 2 Register
0x0340_0918 = 0xE0000000 -- iATU Lower target address offset inbound
0x0340_091C = 0x00000000 -- iATU Upper target address offset inbound

#BAR-1 region-1 as Outbound
0x0340_1014 = 0x00000FFF -- BAR1 mask register
0x0340_0900 = 0x00000001 -- iATU Index register
0x0340_0904 = 0x00000000 -- iATU Region Control 1 Register
0x0340_090C = 0xE1000000 -- iATU Lower base address offset outbound
0x0340_0910 = 0x00000000 -- iATU Upper base address offset outbound
0x0340_0914 = 0xE1000FFF -- iATU Limit address offset outbound
0x0340_0908 = 0x80000000 -- iATU Region Control 2 Register
0x0340_0918 = 0x41800000 -- iATU Lower target address offset outbound
0x0340_091C = 0x00000040 -- iATU Upper target address offset outbound

#BAR-2,3 region-2 as Inbound
0x0340_1018 = 0x00000FFF -- BAR2 mask register
0x0340_0900 = 0x80000002 -- iATU Index register
0x0340_0908 = 0xC0000200 -- iATU Region Control 2 Register
0x0340_0918 = 0x80000000 -- iATU Lower target address offset inbound
0x0340_091C = 0x00000008 -- iATU Upper target address offset inbound

#BAR-4,5 region-3 as Inbound
0x0340_1020 = 0x00000FFF -- BAR4 mask register
0x0340_0900 = 0x80000003 -- iATU Index register
0x0340_0908 = 0xC0000400 -- iATU Region Control 2 Register
0x0340_0918 = 0x81000000 -- iATU Lower target address offset inbound
0x0340_091C = 0x00000008 -- iATU Upper target address offset inbound

Endpoint-2 :

0x5F00_1010 = 0x00000FFF -- BAR0 mask register
0x5F00_0900 = 0x80000000 -- iATU Index register
0x5F00_0904 = 0x00000000 -- iATU Region Control 1 Register
0x5F00_0908 = 0xC0000000 -- iATU Region Control 2 Register
0x5F00_0918 = 0xA0000000 -- iATU Lower target address offset inbound
0x5F00_091C = 0x00000000 -- iATU Upper target address offset inbound



On Root complex side, i can see below information using "lspci -v" command.

00:00.0 PCI bridge: Freescale Semiconductor Inc Device 81c0 (rev 10) (prog-if 00 [Normal decode])
Flags: bus master, fast devsel, latency 0, IRQ 77
Bus: primary=00, secondary=01, subordinate=ff, sec-latency=0
Memory behind bridge: 40000000-433fffff
Prefetchable memory behind bridge: 0000000043400000-00000000434fffff
Capabilities: [40] Power Management version 3
Capabilities: [50] MSI: Enable- Count=1/16 Maskable- 64bit+
Capabilities: [70] Express Root Port (Slot-), MSI 00
Capabilities: [100] Advanced Error Reporting
Capabilities: [148] #19
Kernel driver in use: pcieport
lspci: Unable to load libkmod resources: error -12

01:00.0 PCI bridge: Pericom Semiconductor Device 1224 (prog-if 00 [Normal decode])
Flags: bus master, fast devsel, latency 0, IRQ 78
Memory at 4043000000 (32-bit, non-prefetchable) [size=128K]
Bus: primary=01, secondary=02, subordinate=07, sec-latency=0
Memory behind bridge: 40000000-42ffffff
Prefetchable memory behind bridge: 0000000043400000-00000000434fffff
Capabilities: [40] Power Management version 3
Capabilities: [48] MSI: Enable+ Count=1/1 Maskable- 64bit+
Capabilities: [68] Express Upstream Port, MSI 00
Capabilities: [a4] Subsystem: Pericom Semiconductor Device 1224
Capabilities: [100] Device Serial Number 00-00-00-00-00-00-00-00
Capabilities: [fb4] Advanced Error Reporting
Capabilities: [138] Power Budgeting <?>
Capabilities: [148] Virtual Channel
Capabilities: [270] L1 PM Substates
Capabilities: [900] #12
Kernel driver in use: pcieport

01:00.1 System peripheral: Pericom Semiconductor Device 1224
Subsystem: Pericom Semiconductor Device 1224
Flags: bus master, fast devsel, latency 0
Memory at 4043020000 (32-bit, non-prefetchable)
Capabilities: [40] Power Management version 3
Capabilities: [48] MSI: Enable- Count=1/1 Maskable- 64bit+
Capabilities: [68] Express Endpoint, MSI 00
Capabilities: [a4] Subsystem: Pericom Semiconductor Device 1224
Capabilities: [100] Device Serial Number 00-00-00-00-00-00-00-00
Capabilities: [fb4] Advanced Error Reporting
Capabilities: [138] Power Budgeting <?>
Capabilities: [148] Virtual Channel
Capabilities: [270] L1 PM Substates
Capabilities: [900] #12

02:01.0 PCI bridge: Pericom Semiconductor Device 1224 (prog-if 00 [Normal decode])
Flags: bus master, fast devsel, latency 0, IRQ 79
Bus: primary=02, secondary=03, subordinate=03, sec-latency=0
Capabilities: [40] Power Management version 3
Capabilities: [48] MSI: Enable+ Count=1/1 Maskable- 64bit+
Capabilities: [68] Express Downstream Port (Slot+), MSI 00
Capabilities: [a4] Subsystem: Pericom Semiconductor Device 1224
Capabilities: [100] Device Serial Number 00-00-00-00-00-00-00-00
Capabilities: [fb4] Advanced Error Reporting
Capabilities: [148] Virtual Channel
Capabilities: [520] Access Control Services
Capabilities: [270] L1 PM Substates
Capabilities: [900] #12
Kernel driver in use: pcieport

02:02.0 PCI bridge: Pericom Semiconductor Device 1224 (prog-if 00 [Normal decode])
Flags: bus master, fast devsel, latency 0, IRQ 80
Bus: primary=02, secondary=04, subordinate=04, sec-latency=0
Memory behind bridge: 40000000-417fffff
Prefetchable memory behind bridge: 0000000043400000-00000000434fffff
Capabilities: [40] Power Management version 3
Capabilities: [48] MSI: Enable+ Count=1/1 Maskable- 64bit+
Capabilities: [68] Express Downstream Port (Slot+), MSI 00
Capabilities: [a4] Subsystem: Pericom Semiconductor Device 1224
Capabilities: [100] Device Serial Number 00-00-00-00-00-00-00-00
Capabilities: [fb4] Advanced Error Reporting
Capabilities: [148] Virtual Channel
Capabilities: [520] Access Control Services
Capabilities: [270] L1 PM Substates
Capabilities: [900] #12
Kernel driver in use: pcieport

02:03.0 PCI bridge: Pericom Semiconductor Device 1224 (prog-if 00 [Normal decode])
Flags: bus master, fast devsel, latency 0, IRQ 81
Bus: primary=02, secondary=05, subordinate=05, sec-latency=0
Memory behind bridge: 41800000-42ffffff
Capabilities: [40] Power Management version 3
Capabilities: [48] MSI: Enable+ Count=1/1 Maskable- 64bit+
Capabilities: [68] Express Downstream Port (Slot+), MSI 00
Capabilities: [a4] Subsystem: Pericom Semiconductor Device 1224
Capabilities: [100] Device Serial Number 00-00-00-00-00-00-00-00
Capabilities: [fb4] Advanced Error Reporting
Capabilities: [148] Virtual Channel
Capabilities: [520] Access Control Services
Capabilities: [270] L1 PM Substates
Capabilities: [900] #12
Kernel driver in use: pcieport

02:04.0 PCI bridge: Pericom Semiconductor Device 1224 (prog-if 00 [Normal decode])
Flags: bus master, fast devsel, latency 0, IRQ 82
Bus: primary=02, secondary=06, subordinate=06, sec-latency=0
Capabilities: [40] Power Management version 3
Capabilities: [48] MSI: Enable+ Count=1/1 Maskable- 64bit+
Capabilities: [68] Express Downstream Port (Slot+), MSI 00
Capabilities: [a4] Subsystem: Pericom Semiconductor Device 1224
Capabilities: [100] Device Serial Number 00-00-00-00-00-00-00-00
Capabilities: [fb4] Advanced Error Reporting
Capabilities: [148] Virtual Channel
Capabilities: [520] Access Control Services
Capabilities: [270] L1 PM Substates
Capabilities: [900] #12
Kernel driver in use: pcieport

02:05.0 PCI bridge: Pericom Semiconductor Device 1224 (prog-if 00 [Normal decode])
Flags: bus master, fast devsel, latency 0, IRQ 83
Bus: primary=02, secondary=07, subordinate=07, sec-latency=0
Capabilities: [40] Power Management version 3
Capabilities: [48] MSI: Enable+ Count=1/1 Maskable- 64bit+
Capabilities: [68] Express Downstream Port (Slot+), MSI 00
Capabilities: [a4] Subsystem: Pericom Semiconductor Device 1224
Capabilities: [100] Device Serial Number 00-00-00-00-00-00-00-00
Capabilities: [fb4] Advanced Error Reporting
Capabilities: [148] Virtual Channel
Capabilities: [520] Access Control Services
Capabilities: [270] L1 PM Substates
Capabilities: [900] #12
Kernel driver in use: pcieport

04:00.0 Power PC: Freescale Semiconductor Inc Device 81c0 (rev 10)
Flags: bus master, fast devsel, latency 0, IRQ 84
Memory at 4041000000 (32-bit, non-prefetchable) [size=4K]
Memory at 4041001000 (32-bit, non-prefetchable) [size=4K]
Memory at 4043400000 (64-bit, prefetchable) [size=4K]
Memory at 4043401000 (64-bit, prefetchable) [size=4K]
Expansion ROM at 4040000000 [disabled] [size=16M]
Capabilities: [40] Power Management version 3
Capabilities: [50] MSI: Enable+ Count=1/16 Maskable- 64bit+
Capabilities: [70] Express Endpoint, MSI 00
Capabilities: [100] Advanced Error Reporting
Capabilities: [148] #19
Capabilities: [168] Address Translation Service (ATS)

05:00.0 Power PC: Freescale Semiconductor Inc Device 0000 (rev 01)
Flags: bus master, fast devsel, latency 0, IRQ 85
Memory at 4041800000 (32-bit, non-prefetchable) [size=4K]
Expansion ROM at 4042000000 [disabled] [size=16M]
Capabilities: [40] Power Management version 3
Capabilities: [50] MSI: Enable+ Count=1/16 Maskable- 64bit+
Capabilities: [70] Express Endpoint, MSI 00
Capabilities: [100] Advanced Error Reporting
Capabilities: [148] #19
Capabilities: [158] Address Translation Service (ATS)
Capabilities: [168] L1 PM Substates



Here in the above,

04:00.0 is Endpoint-1 and 05:00.0 is Endpoint-2.

As per my understanding,

I am writing to address 0xE100_0000 which is iATU base address offset outbound (Upper, Lower) of BAR1 in Endpoint-1. 0xE100_0000 after address translation is 0x40_4180_0000 which is the iATU Target address (upper, lower).

So the data written to 0xE100_0000 should go to 0x40_4180_0000 which is the base address (BAR) of Endpoint-2 (05:00.0).

Again as per the Inbound translation (BAR match mode) in Endpoint-2, data received from 0x40_4180_0000 should go to 0xA000_0000 which is iATU Target address offset inbound (Upper, Lower)

But I don't see it working as expected. Please firstly let me know, Is my understanding correct ?

Thanks.
 


TRINATH KARRI said:
Hi,

I have a PCIe Rootcomplex (Custom LS1046A board configured as RC), Endpoint-1 (Custom LS1046A board configured as EP) and Endpoint-2 (Custom IMX8QM board configured as EP). Endpoints are connected to the Root complex through switch (PI7C9X2G1224GP).

I want to perform Endpoint-1 to Endpoint-2 data transfer. For that, i configured ATU registers of Endpoint-1 and Endpoint-2 as mentioned below.

Endpoint-1:

#BAR-0 region-0 as Inbound
0x0340_1010 = 0x00000FFF -- BAR0 mask register
0x0340_0900 = 0x80000000 -- iATU Index register
0x0340_0908 = 0xC0000000 -- iATU Region Control 2 Register
0x0340_0918 = 0xE0000000 -- iATU Lower target address offset inbound
0x0340_091C = 0x00000000 -- iATU Upper target address offset inbound

#BAR-1 region-1 as Outbound
0x0340_1014 = 0x00000FFF -- BAR1 mask register
0x0340_0900 = 0x00000001 -- iATU Index register
0x0340_0904 = 0x00000000 -- iATU Region Control 1 Register
0x0340_090C = 0xE1000000 -- iATU Lower base address offset outbound
0x0340_0910 = 0x00000000 -- iATU Upper base address offset outbound
0x0340_0914 = 0xE1000FFF -- iATU Limit address offset outbound
0x0340_0908 = 0x80000000 -- iATU Region Control 2 Register
0x0340_0918 = 0x41800000 -- iATU Lower target address offset outbound
0x0340_091C = 0x00000040 -- iATU Upper target address offset outbound

#BAR-2,3 region-2 as Inbound
0x0340_1018 = 0x00000FFF -- BAR2 mask register
0x0340_0900 = 0x80000002 -- iATU Index register
0x0340_0908 = 0xC0000200 -- iATU Region Control 2 Register
0x0340_0918 = 0x80000000 -- iATU Lower target address offset inbound
0x0340_091C = 0x00000008 -- iATU Upper target address offset inbound

#BAR-4,5 region-3 as Inbound
0x0340_1020 = 0x00000FFF -- BAR4 mask register
0x0340_0900 = 0x80000003 -- iATU Index register
0x0340_0908 = 0xC0000400 -- iATU Region Control 2 Register
0x0340_0918 = 0x81000000 -- iATU Lower target address offset inbound
0x0340_091C = 0x00000008 -- iATU Upper target address offset inbound

Endpoint-2 :

0x5F00_1010 = 0x00000FFF -- BAR0 mask register
0x5F00_0900 = 0x80000000 -- iATU Index register
0x5F00_0904 = 0x00000000 -- iATU Region Control 1 Register
0x5F00_0908 = 0xC0000000 -- iATU Region Control 2 Register
0x5F00_0918 = 0xA0000000 -- iATU Lower target address offset inbound
0x5F00_091C = 0x00000000 -- iATU Upper target address offset inbound



On Root complex side, i can see below information using "lspci -v" command.

00:00.0 PCI bridge: Freescale Semiconductor Inc Device 81c0 (rev 10) (prog-if 00 [Normal decode])
Flags: bus master, fast devsel, latency 0, IRQ 77
Bus: primary=00, secondary=01, subordinate=ff, sec-latency=0
Memory behind bridge: 40000000-433fffff
Prefetchable memory behind bridge: 0000000043400000-00000000434fffff
Capabilities: [40] Power Management version 3
Capabilities: [50] MSI: Enable- Count=1/16 Maskable- 64bit+
Capabilities: [70] Express Root Port (Slot-), MSI 00
Capabilities: [100] Advanced Error Reporting
Capabilities: [148] #19
Kernel driver in use: pcieport
lspci: Unable to load libkmod resources: error -12

01:00.0 PCI bridge: Pericom Semiconductor Device 1224 (prog-if 00 [Normal decode])
Flags: bus master, fast devsel, latency 0, IRQ 78
Memory at 4043000000 (32-bit, non-prefetchable) [size=128K]
Bus: primary=01, secondary=02, subordinate=07, sec-latency=0
Memory behind bridge: 40000000-42ffffff
Prefetchable memory behind bridge: 0000000043400000-00000000434fffff
Capabilities: [40] Power Management version 3
Capabilities: [48] MSI: Enable+ Count=1/1 Maskable- 64bit+
Capabilities: [68] Express Upstream Port, MSI 00
Capabilities: [a4] Subsystem: Pericom Semiconductor Device 1224
Capabilities: [100] Device Serial Number 00-00-00-00-00-00-00-00
Capabilities: [fb4] Advanced Error Reporting
Capabilities: [138] Power Budgeting <?>
Capabilities: [148] Virtual Channel
Capabilities: [270] L1 PM Substates
Capabilities: [900] #12
Kernel driver in use: pcieport

01:00.1 System peripheral: Pericom Semiconductor Device 1224
Subsystem: Pericom Semiconductor Device 1224
Flags: bus master, fast devsel, latency 0
Memory at 4043020000 (32-bit, non-prefetchable)
Capabilities: [40] Power Management version 3
Capabilities: [48] MSI: Enable- Count=1/1 Maskable- 64bit+
Capabilities: [68] Express Endpoint, MSI 00
Capabilities: [a4] Subsystem: Pericom Semiconductor Device 1224
Capabilities: [100] Device Serial Number 00-00-00-00-00-00-00-00
Capabilities: [fb4] Advanced Error Reporting
Capabilities: [138] Power Budgeting <?>
Capabilities: [148] Virtual Channel
Capabilities: [270] L1 PM Substates
Capabilities: [900] #12

02:01.0 PCI bridge: Pericom Semiconductor Device 1224 (prog-if 00 [Normal decode])
Flags: bus master, fast devsel, latency 0, IRQ 79
Bus: primary=02, secondary=03, subordinate=03, sec-latency=0
Capabilities: [40] Power Management version 3
Capabilities: [48] MSI: Enable+ Count=1/1 Maskable- 64bit+
Capabilities: [68] Express Downstream Port (Slot+), MSI 00
Capabilities: [a4] Subsystem: Pericom Semiconductor Device 1224
Capabilities: [100] Device Serial Number 00-00-00-00-00-00-00-00
Capabilities: [fb4] Advanced Error Reporting
Capabilities: [148] Virtual Channel
Capabilities: [520] Access Control Services
Capabilities: [270] L1 PM Substates
Capabilities: [900] #12
Kernel driver in use: pcieport

02:02.0 PCI bridge: Pericom Semiconductor Device 1224 (prog-if 00 [Normal decode])
Flags: bus master, fast devsel, latency 0, IRQ 80
Bus: primary=02, secondary=04, subordinate=04, sec-latency=0
Memory behind bridge: 40000000-417fffff
Prefetchable memory behind bridge: 0000000043400000-00000000434fffff
Capabilities: [40] Power Management version 3
Capabilities: [48] MSI: Enable+ Count=1/1 Maskable- 64bit+
Capabilities: [68] Express Downstream Port (Slot+), MSI 00
Capabilities: [a4] Subsystem: Pericom Semiconductor Device 1224
Capabilities: [100] Device Serial Number 00-00-00-00-00-00-00-00
Capabilities: [fb4] Advanced Error Reporting
Capabilities: [148] Virtual Channel
Capabilities: [520] Access Control Services
Capabilities: [270] L1 PM Substates
Capabilities: [900] #12
Kernel driver in use: pcieport

02:03.0 PCI bridge: Pericom Semiconductor Device 1224 (prog-if 00 [Normal decode])
Flags: bus master, fast devsel, latency 0, IRQ 81
Bus: primary=02, secondary=05, subordinate=05, sec-latency=0
Memory behind bridge: 41800000-42ffffff
Capabilities: [40] Power Management version 3
Capabilities: [48] MSI: Enable+ Count=1/1 Maskable- 64bit+
Capabilities: [68] Express Downstream Port (Slot+), MSI 00
Capabilities: [a4] Subsystem: Pericom Semiconductor Device 1224
Capabilities: [100] Device Serial Number 00-00-00-00-00-00-00-00
Capabilities: [fb4] Advanced Error Reporting
Capabilities: [148] Virtual Channel
Capabilities: [520] Access Control Services
Capabilities: [270] L1 PM Substates
Capabilities: [900] #12
Kernel driver in use: pcieport

02:04.0 PCI bridge: Pericom Semiconductor Device 1224 (prog-if 00 [Normal decode])
Flags: bus master, fast devsel, latency 0, IRQ 82
Bus: primary=02, secondary=06, subordinate=06, sec-latency=0
Capabilities: [40] Power Management version 3
Capabilities: [48] MSI: Enable+ Count=1/1 Maskable- 64bit+
Capabilities: [68] Express Downstream Port (Slot+), MSI 00
Capabilities: [a4] Subsystem: Pericom Semiconductor Device 1224
Capabilities: [100] Device Serial Number 00-00-00-00-00-00-00-00
Capabilities: [fb4] Advanced Error Reporting
Capabilities: [148] Virtual Channel
Capabilities: [520] Access Control Services
Capabilities: [270] L1 PM Substates
Capabilities: [900] #12
Kernel driver in use: pcieport

02:05.0 PCI bridge: Pericom Semiconductor Device 1224 (prog-if 00 [Normal decode])
Flags: bus master, fast devsel, latency 0, IRQ 83
Bus: primary=02, secondary=07, subordinate=07, sec-latency=0
Capabilities: [40] Power Management version 3
Capabilities: [48] MSI: Enable+ Count=1/1 Maskable- 64bit+
Capabilities: [68] Express Downstream Port (Slot+), MSI 00
Capabilities: [a4] Subsystem: Pericom Semiconductor Device 1224
Capabilities: [100] Device Serial Number 00-00-00-00-00-00-00-00
Capabilities: [fb4] Advanced Error Reporting
Capabilities: [148] Virtual Channel
Capabilities: [520] Access Control Services
Capabilities: [270] L1 PM Substates
Capabilities: [900] #12
Kernel driver in use: pcieport

04:00.0 Power PC: Freescale Semiconductor Inc Device 81c0 (rev 10)
Flags: bus master, fast devsel, latency 0, IRQ 84
Memory at 4041000000 (32-bit, non-prefetchable) [size=4K]
Memory at 4041001000 (32-bit, non-prefetchable) [size=4K]
Memory at 4043400000 (64-bit, prefetchable) [size=4K]
Memory at 4043401000 (64-bit, prefetchable) [size=4K]
Expansion ROM at 4040000000 [disabled] [size=16M]
Capabilities: [40] Power Management version 3
Capabilities: [50] MSI: Enable+ Count=1/16 Maskable- 64bit+
Capabilities: [70] Express Endpoint, MSI 00
Capabilities: [100] Advanced Error Reporting
Capabilities: [148] #19
Capabilities: [168] Address Translation Service (ATS)

05:00.0 Power PC: Freescale Semiconductor Inc Device 0000 (rev 01)
Flags: bus master, fast devsel, latency 0, IRQ 85
Memory at 4041800000 (32-bit, non-prefetchable) [size=4K]
Expansion ROM at 4042000000 [disabled] [size=16M]
Capabilities: [40] Power Management version 3
Capabilities: [50] MSI: Enable+ Count=1/16 Maskable- 64bit+
Capabilities: [70] Express Endpoint, MSI 00
Capabilities: [100] Advanced Error Reporting
Capabilities: [148] #19
Capabilities: [158] Address Translation Service (ATS)
Capabilities: [168] L1 PM Substates



Here in the above,

04:00.0 is Endpoint-1 and 05:00.0 is Endpoint-2.

As per my understanding,

I am writing to address 0xE100_0000 which is iATU base address offset outbound (Upper, Lower) of BAR1 in Endpoint-1. 0xE100_0000 after address translation is 0x40_4180_0000 which is the iATU Target address (upper, lower).

So the data written to 0xE100_0000 should go to 0x40_4180_0000 which is the base address (BAR) of Endpoint-2 (05:00.0).

Again as per the Inbound translation (BAR match mode) in Endpoint-2, data received from 0x40_4180_0000 should go to 0xA000_0000 which is iATU Target address offset inbound (Upper, Lower)

But I don't see it working as expected. Please firstly let me know, Is my understanding correct ?

Thanks.
Click to expand...
Hey there!

From what I can see, your understanding seems to be on the right track. You have configured the ATU registers for Endpoint-1 and Endpoint-2 to perform data transfer between them. The base address offset outbound of BAR1 in Endpoint-1 is set to 0xE100_0000, which should translate to the target address 0x40_4180_0000 in Endpoint-2. And the inbound translation in Endpoint-2 should receive the data at 0x40_4180_0000 and place it at 0xA000_0000.

However, if it's not working as expected, there could be a couple of things to check. First, make sure that the ATU registers are being correctly programmed and the translation is happening as intended. You can double-check the register values and try reconfiguring them if necessary.

Another thing to consider is the configuration of the switch (PI7C9X2G1224GP) between the endpoints and the root complex. Make sure that the switch is properly routing the PCIe transactions between the endpoints and the root complex.

If you have already verified these aspects and are still facing issues, it would be helpful to provide more information about the specific problem you are encountering.
 
Hi @TuxBot ,
I have tested RC to EP transactions using switch. They are working fine. Is there anything i need to check in switch esp., for endpoint to endpoint transactions ?
 
TRINATH KARRI said:
Hi @TuxBot ,
I have tested RC to EP transactions using switch. They are working fine. Is there anything i need to check in switch esp., for endpoint to endpoint transactions ?
Click to expand...
Hey there!

If your Root Complex (RC) to Endpoint (EP) transactions are working fine with the switch, that's a good sign! However, when it comes to Endpoint-to-Endpoint transactions, there are a few things you can check in the switch configuration:

1. Make sure that the switch is properly configured to allow Endpoint-to-Endpoint transactions. Some switches have specific settings or configurations that need to be enabled to support direct communication between endpoints.

2. Verify that the switch is correctly routing the transactions between the two endpoints. The switch should be able to properly forward the transactions from one endpoint to the other without any interference or blocking.

3. Check if there are any specific rules or policies in the switch for handling Endpoint-to-Endpoint transactions. Some switches may have specific rules or policies that need to be configured to allow these transactions.

If you have access to the switch configuration, review its documentation and look for any specific settings related to Endpoint-to-Endpoint communication. If all else fails or you're uncertain about the switch configuration, reaching out to the switch manufacturer's support or consulting their documentation for guidance would be a great idea.

Hope this helps! Let me know if you have any other questions.
 
TuxBot said:
Hey there!

If your Root Complex (RC) to Endpoint (EP) transactions are working fine with the switch, that's a good sign! However, when it comes to Endpoint-to-Endpoint transactions, there are a few things you can check in the switch configuration:

1. Make sure that the switch is properly configured to allow Endpoint-to-Endpoint transactions. Some switches have specific settings or configurations that need to be enabled to support direct communication between endpoints.

2. Verify that the switch is correctly routing the transactions between the two endpoints. The switch should be able to properly forward the transactions from one endpoint to the other without any interference or blocking.

3. Check if there are any specific rules or policies in the switch for handling Endpoint-to-Endpoint transactions. Some switches may have specific rules or policies that need to be configured to allow these transactions.

If you have access to the switch configuration, review its documentation and look for any specific settings related to Endpoint-to-Endpoint communication. If all else fails or you're uncertain about the switch configuration, reaching out to the switch manufacturer's support or consulting their documentation for guidance would be a great idea.

Hope this helps! Let me know if you have any other questions.
Click to expand...
@TuxBot Yeah sure. i will check switch settings. Thanks a lot.
 
@TuxBot Please read my query clearly and try to answer. Do you think, below configuration is correct in EP1

0x0340_1014 = 0x00000FFF -- BAR1 mask register
0x0340_0900 = 0x00000001 -- iATU Index register
0x0340_0904 = 0x00000000 -- iATU Region Control 1 Register
0x0340_090C = 0xE1000000 -- iATU Lower base address offset outbound
0x0340_0910 = 0x00000000 -- iATU Upper base address offset outbound
0x0340_0914 = 0xE1000FFF -- iATU Limit address offset outbound
0x0340_0908 = 0x80000000 -- iATU Region Control 2 Register
0x0340_0918 = 0x41800000 -- iATU Lower target address offset outbound
0x0340_091C = 0x00000040 -- iATU Upper target address offset outbound
 
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