My OSS friendly CPU project

G

goran dakov

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I am currently making a Computer Processor in verilog language. It will feature Open Source firmware and have a translator to x86_64. It will be very wide, with 9 instructions executed at the same time, and with out-of-order execution. Check out the Kickstarter campaign: Just type in "heptane" at the kickstarter website.

I'm posting this since your forum doesn't seem to have rules against it :)
 


I've already began a GCC port and gnu binutils port. Basic instructions are ready in GCC, but i havent yet figured out how to delete instructions from the .md file. When I delete e.g. shld/shrd i get compilation errors.
 
An update on my OoO 9-wide cpu: It will now be released under a bsd-like license with additional 5-th clause requiring additional permission to implement as a chip. Simulation and modification is allowed, as well as synthesis. It is not yet complete, but already has load, store, alu operations. The store to load forwarding is not yet debugged but is mostly completed. Implementation of integer simd exists but is not debugged. FPU support is in development. The emulation target for now is set to be assembly source code, that is, a subset of x86_64 asm will be supported by the gas port. Some cisc instructions are assembled as multi instruction sequences.
 
Welcome back to linux.org, @Goran Dakov :)

This project's scope is beyond my "paygrade", but I wish you luck with your venture.

wizardfromoz
 
Currently my CPU architecture will be immune to meltdown/spectre. This is due to bounds checked pointers. They have 44 address bits, 7 high and low bounds (each) and 5 bit bound exponent. There is also an "on low bound" bit. An extra bit per 64 bits is used to indicate a pointer (stored in ECC memory bits) so it is effectively a 65 bit architecture. This prevents pointers from being written to memory by reading file or internet socket.
 
I'm going to have to backpedal on writing an emulator of another ISA as it is now super complicated with hardware vectorization and 120 isue for for loop like code but the SIMD is effectively 64 bit with 136 bit registers and the 128 bit instructions take 2 units.
Theoretically it is possible to do base amd64 with the "hardware loop unroller" but i'm not going to write the translator.
The 120 issue is only available with the hardware loop unroller, otherwise it is still 10 and sometimes 30 in a special mode, but this is mainly useful for code that fills in data structures.
 
I'm going to have to backpedal on commercial licensing as well. Its GPL 3.0 now and unfinished but feature complete.
 
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