My 9 issue disvliw CPU under TAPR open hardware license

Goran Dakov

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The heptane CPU that i'm implementing in my own time is a 9-issue risc-like cpu with "bundleisation" e.g. code comes in 32-byte chunks with variable length instructions made up of 2 byte parcels.
I decided to make it open source under the TAPR open hardware license. The copying.txt file has been changed (rtl folder only) but i'm not currently making it available for public download.
The current stage of development is : ALU only fuzzing - passed (randomly generated ALU instructions, ran it for about 1000000 instructions)
ALU and LOAD fuzzing: in progress
ALU, LOAD and STORE fuzzing: not started yet
Memory adressing modes inspired by x86_64 (but no CISC instructions)
Low fat pointers with 7 bit precision of the bounds (64-bit) and no penalty for bounds checking during load/store
But there is penalty for memory allocation and restrictions on alignment of the allocated memory chunks.
Although to be fair if there is no jump instructions in a issue-window the IPC would often reduce to 8.
 
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