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    My 9 issue disvliw CPU under TAPR open hardware license

    The heptane CPU that i'm implementing in my own time is a 9-issue risc-like cpu with "bundleisation" e.g. code comes in 32-byte chunks with variable length instructions made up of 2 byte parcels. I decided to make it open source under the TAPR open hardware license. The copying.txt file has been...
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    My OSS friendly CPU project

    I'm considering re-targetting translation from x86_64 to Risc-V.
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    Dual use tecnology restricions by USA and the GPL To be fair, the article says nothing about software, so it might not be included in the dual use technology definition.
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    Dual use tecnology restricions by USA and the GPL

    If the USA creates restrictions on dual use technology, wouldn't that make it illegal for US companies to license their code under the GPL? After all, the GPL license includes People's Republic of China, and how to decide, for example, if the linux kernel is a dual use tecnology? But even if...
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    My OSS friendly CPU project

    Currently my CPU architecture will be immune to meltdown/spectre. This is due to bounds checked pointers. They have 44 address bits, 7 high and low bounds (each) and 5 bit bound exponent. There is also an "on low bound" bit. An extra bit per 64 bits is used to indicate a pointer (stored in ECC...
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    My OSS friendly CPU project

    An update on my OoO 9-wide cpu: It will now be released under a bsd-like license with additional 5-th clause requiring additional permission to implement as a chip. Simulation and modification is allowed, as well as synthesis. It is not yet complete, but already has load, store, alu operations...