Linux+: Hardware Part 03

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  1. Jarret W. Buse

    Jarret W. Buse Well-Known Member Staff Writer

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    Linux+: Hardware Part 03 - RAM

    The next major piece of hardware after the Central Processing Unit (CPU) is the Random Access Memory (RAM). Basically, the RAM is where data and programs are stored when not being executed by the CPU. The ‘memory’ is considered volatile since it requires electricity to maintain the data in the memory chips. Once power is removed from the system, such as the power button is pushed, data in the RAM is lost. The RAM will hold the Linux Operating System (OS), drivers, applications and data.

    RAM is called Random Access since the data is not stored sequentially like on a backup tape, but in chunks in random areas. When a memory area is needed, the area is allocated based on the availability of an area being unused. When allocated, the area is taken by a program and used by it until it is terminated. When a program ends or the memory allocation is no longer needed, it is unallocated and made available for other programs. Memory may be allocated when the program starts new processes such as a virus scanner checking for an update. Word processing programs will hold a document in the RAM as it is being modified on the screen.

    NOTE: The more RAM a system has, the better it can operate and run applications.

    Before we get into the RAM types, let’s look into the different features a RAM chip can have to differ from the other RAM chips.

    RAM speed is measured in nanoseconds (ns). Slower RAM chips can have a speed over 100 nanoseconds while faster RAM chips are less than 100 ns.

    RAM chips also have a wait state. The wait state is the time it takes a RAM chip to respond to a CPU request. Processor speeds are very fast and RAM speeds are slower so there is a lag, or wait time between the CPU request and the RAM response. Newer processors can actually take a ‘break’ and conserve energy as well as extend the battery life of portable systems. Each cycle waiting for the RAM to respond is a wait state.

    Data is stored in rows and columns within a RAM chip in small capacitors. Capacitors are like small batteries. They can hold a charge which represents a binary value of 1. When the capacitor has no charge, it is considered a binary 0. When data is requested, the specific row must be accessed. When a new row is needed for accessing, it takes time to initialize the new row. When data exists within the same row that has previously been accessed, it is called a ‘page’. In this instance, the time to access the second bit of data will take less time since the row has already been initialized. For instance, it may take 5 clock cycles to activate a row and access data. If a page occurs, the second bit of data may only require 3 clock cycles and the fetch would be 5-3. Larger pages can exist such as 6-4-4-4.

    RAM bus speed is sometimes measured in Megahertz (MHz). When a RAM chip is rated in MHz, it is the bus speed. The data buses on the motherboard are the wires allowing data to flow between components such as the CPU and RAM. If the RAM bus speed matches the motherboard bus speed, then the RAM chips can send data along the buses at the best speed. If the RAM bus speed is slower, then the RAM chips can send data at a slower than normal rate. If the RAM bus speed is faster than the system bus speed, then the RAM is wasting time by being required to slow itself down to match the system bus.

    The refresh rate is the time needed to send power to a row of cells to make sure the capacitor retains the bit values. If power is not cycled through the capacitors, the energy will dissipate and the data is lost. An average of 64 ns is required to pass electricity through the rows. It is possible to go a few minutes and retain the data, but this is not suggested.

    Parity can be important for DRAM chips. Radiation from within the PC can cause capacitors to spontaneously ‘flip’ its charge. A bit turned ‘on’ may suddenly be ‘off’ and vice versa. Each 64-bit section of capacitors has a parity bit. The parity bit is enabled if there are either an even or odd number of bits turned ‘on’. Even-parity enables the parity bit when an even number of bits are on and odd-parity turns on the parity bit when an odd number of bits are ‘on’. When an error is found, a ‘Parity Error’ is generated. When Error Correction Control (ECC) is used, a code is used to generate an ECC value for each set of bits. When one bit is changed, the ECC value becomes invalid and the code can determine which bit has been switched. The corrupted bit can then be switched back and corrected. If two bits are switched, the ECC can detect the error, but not correct it. Correction can only be made with one bit change.

    Interleaving is when two separate banks of chips on a RAM chip can nearly work simultaneously. When one bank of chips is being accessed, another is being prepared to be accessed.

    Pipelining allows for data to be retrieved while previous data is being sent to the CPU.

    There are five basic types of RAM chips:

    1. Dynamic RAM (DRAM)
    2. Synchronous Dynamic RAM (SDRAM)
    3. Fast Page Mode RAM (FPM RAM)
    4. Extended Data Output RAM (EDO RAM)
    5. Direct Rambus DRAM (DRDRAM)
    Dynamic RAM (DRAM)

    With DRAM chips, each capacitor has one transistor meaning there is one capacitor and transistor per storage bit. A DRAM chip with a capacity of 1 MB would have 1 million capacitors and transistors on a single chip.

    Synchronous Dynamic RAM (SDRAM)
    With SDRAM, the RAM chips are synchronized to match the system clock speed with the RAM Bus Speed.

    SDRAM uses interleaving and pipelining to enhance its throughput.

    Fast Page Mode RAM (FPM RAM)

    FPM RAM uses the technology to handle page reads. Here, the row is kept open for access and more data can be read in a faster time by not having to re-access the row. The technique is called a ‘page’.

    Extended Data Output RAM (EDO RAM)

    EDO RAM is an enhancement to the FPM RAM. It uses the ‘page’ technique but also uses a two stage pipeline. Data can be read while the chip is reset for the next read.

    EDO RAM does not work well with higher bus speeds.

    Direct Rambus DRAM (DRDRAM)

    The DRDRAM requires a Direct Rambus Channel which can operate at higher rates than the rest of the motherboard.


    DRDRAM is not supported due to high costs.

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    Last edited: Jan 14, 2014
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